Selectively Doped III-nitride High Electron Mobility Transistor

Description:

Reference #:  00934

 

Background:

University of South Carolina (USC) has pioneered the development of AlInGaN based insulating gate heterojunction field-effect-transistors. This includes AlGaN (barrier)/GaN (channel), AlGaN (barrier)/InGaN (channel) and AlInGaN (lattice matched barrier)/GaN (channel) devices. In addition, the University was the first to report on AlGaN-GaN and AlGaN-GaN-InGaN (back barrier) double heterojunction-field-effect-transistors (DHFETs).  The research team at USC also fabricated E-mode HFETs with AlGaN-GaN HFETs using the conventional fluorine based gate recessing process.

 

Invention Description:

The current invention involves a new device design approach for the development of III-nitride HFETs using a new Selective Area Pulsed Growth (SAG) process. Several other new approaches are also proposed for the device processing steps to mitigate leakage current and breakdown issues.

The new device design approach employs selective area deposition of the AlInN materials using an oxide mask thereby avoiding the high-power fluorine etch that is the root cause of material damage, increase in leakage currents and pre-mature breakdown of the AlInN-GaN HFETs.  An innovative pulsed-epitaxy approach was also used to improve material quality and allow for a precise control of the spacer and barrier thicknesses. 

In addition to a the selective area deposited device design and the new pulsed materials deposition approach, a newly developed low-power PECVD process for the deposition of the conformal gate insulators was utilized to avoid side-wall leakage in E-mode devices. 

The main innovations arising from this invention include:

1.       Selective area re-growth of the source-drain and channel region to create the gate recess.

2.       Growth of low-defect buffer and channel layers (GaN) using pulsed lateral overgrowth process and pulsed atomic layer epitaxy.

3.       Selective area doping procedure to reduce the access resistances.

4.       Digital pulsed deposition of insulator layers to avoid gate leakage and premature surface breakdown.

5.       A new polymer based surface passivation to avoid plasma related surface damage.

6.       Exploration of a new in situ CVD deposited pulsed AlN layer for surface passivation.

7.       Extremely low power plasma enhanced CVD of fluorine to modulate the threshold voltage.

8.       Exploration of field-plated enhancement mode structures.

9.       Exploration of low power PECVD deposited SiO2/SiN for the insulating gate E-mode devices.

 

Advantages and Benefits:

The new process is very helpful in reducing current-slump and avoiding surface leakage and premature breakdown.

 

Potential Applications:

Design of III-nitride heterojunction field-effect-transistors (HFETs)

 

Patent Information:
For Information, Contact:
Technology Commercialization
University of South Carolina
technology@sc.edu
Inventors:
Asif Khan
Qhalid Fareed
Vinod Adivarahan
Keywords:
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